Signal quality indicator

ABSTRACT

A method for measuring quality of a stream of data, which was transmitted in accordance with a transmit clock, the method consisting of generating samples of the stream of data at sample times determined in accordance with a receive clock, and averaging values of the samples so as to generate a metric indicative of the quality of the stream of data. The receive clock is characterized as operating independently of the transmit clock.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional PatentApplications No. 60/341,525, filed Dec. 17, 2001 and 60/345,483, filedJan. 3, 2002, which are incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates generally to data communication,and specifically to converting between serial and parallel data.

BACKGROUND OF THE INVENTION

[0003] Conversion of parallel data to serial data, termed serialization,and the converse operation, deserialization, are required for many datacommunication processes. The parallel data is generated on a bus, and isconverted to serial data for transmission on one channel. As bussesincrease in width, typical busses having 64 lines or even more, thespeed at which data which has been serialized needs to be transmittedmust of necessity increase, to avoid data build-up at the serializerinterface. Serial data rates of Gigabits/s are typically required toavoid the build-up. Multichannel SERDES (serializer-deserializer)devices comprise multiple serializers each having a serializerinterface. Each interface generates a channel of serial data which isthen transmitted to a receiver.

[0004] Recovery of such high speed multichannel serialized data presentsconsiderable problems at the receiver. In systems known in the art aclock is recovered for each channel of the received data, and each clockis used to sample the received data. Typically, each recovered clock islocked to its own phase locked loop (PLL) oscillator. Furthermore,multiple sampling PLL clocks require respective elastic buffers forstoring the sampled data, and there is typically an extra PLL clock forsynchronizing all the sampling clocks to a common local clock.

[0005] However, each PLL may suffer from its own jitter, since it islocked to incoming data; in addition, problems are caused by themultiplicity of PLL clocks. The PLL is a highly sensitive circuit, sothat in layout of a device having PLLs, each PLL is, for example,isolated as much as possible and has its own ground and supply lines.Devices requiring multiple PLL oscillators thus require more area andmore pins, and typically give lower yields because one PLL failurecauses device failure.

[0006] Data which is initially in an 8-bit (8 b) form is typicallyencoded at the transmitter into an alternative form so that errors inthe received data may be detected. An IEEE standard 802.3 z, publishedby the Institute of Electronic and Electrical Engineers, New York, N.Y.,describes an 8 b/10 b coding scheme, originally developed by IBMCorporation. Using the scheme, a transmitter maintains a table having aone-to-two correspondence, so that each 8 b word may be transmitted asone of two 10 b words. Each 10 b word in the table has between 4 and 6ones (and correspondingly 6 and 4 zeroes). A partial list of 8 b andcorresponding 10 b words, according to the scheme, is shown in Table Ibelow. TABLE I First Second Running Decimal mapping B1 mapping B2Disparity 8-bit word value (RD−) (RD+) (RD) 00000000  0 100111 0100011000 1011 same 00000001  1 011101 0100 100010 1011 same 00000010  2101101 0100 010010 1011 same 00000011  3 110001 1011 110001 0100 switch00000100  4 110101 0100 001010 1011 same 00000101  5 101001 1011 1010010100 switch 00000110  6 011001 1011 011001 0100 switch 00000111  7111000 1011 000111 0100 switch 00001000  8 111001 0100 000110 1011 same00001001  9 100101 1011 100101 0100 switch . . . . . . . . . . . . . . .10111100 188 001110 1010 001110 1010 same 10111101 189 101110 1010010001 1010 switch . . . . . . . . . . . . . . . 11000100 196 1101010110 001010 0110 switch . . . . . . . . . . . . . . . 11100100 228110101 0001 001010 1110 same . . . . . . . . . . . . . . . 11111111 255101011 0001 010100 1110 same

[0007] A complete listing of Table I comprises 256 rows. As shown inTable I, each 8 b word is mapped to one of two 10 b words. The firstmapping B1 comprises words having 5 or 6 ones. The second mapping B2comprises words having 4 or 5 ones. In transmitting a string of 8 bwords, a transmitter calculates a total running disparity (RD) of thestring—the difference between the total number of ones and the totalnumber of zeroes transmitted. After each 10 b word has been transmitted,the transmitter evaluates if RD is positive, negative, or zero. For RD+the following 10 b word is transmitted from the first mapping B1, andfor RD− the following 10 b word is transmitted from the second mappingB2. If RD is zero, the fourth column, stating whether the same mappingis used or if the mapping switches, is used. The transmitter is thusable to maintain the disparity of the transmitted string within thebounds of +1 and −1.

[0008] A receiver of the encoded data is able to use the disparityproperties to detect if there are errors in the received data.Typically, the receiver calculates and updates a disparity status of thereceived string, and if this results in a value outside the bounds, thereceiver knows that there is an error in the received data. Similarly,in receiving any two sequential 10 b words, if the instruction in columnfour is violated, there is an error in the received data. However, inmost cases the receiver is not able to know in exactly which receivedword the error occurred. Even if it does know the exact word, thereceiver is not able to correct the error.

[0009] Performance of both data transmitters and data receivers is animportant factor in their operation. One of the measurements ofperformance is signal quality, both transmitted signal quality andreceived signal quality. A method for measuring signal quality, known inthe art, is by generating an “eye” pattern. The eye pattern may begenerated in specialized equipment by repeatedly sampling the signallevel and plotting the level on a vertical axis, while triggering ahorizontal axis to a signal clock. A “perfect” signal would give arectangle, and the quality of the actual signal is proportional to the“openness” of the eye pattern generated—the more open the center of theeye, the higher the signal quality.

[0010] The specialized equipment for generating eye patterns may beavailable in a facility where the transmitter and/or receiver areproduced, so that adjustments to the transmitter and/or receiver may bemade at the facility to improve signal quality. However, such signalquality measurements and adjustments to improve the quality may not beable to be made in an “on-site” situation, because of the lack ofspecialized equipment. There is thus a need for a signal qualityindicator that overcomes these problems.

SUMMARY OF THE INVENTION

[0011] It is an object of some aspects of the present invention toprovide a signal quality indicator.

[0012] In preferred embodiments of the present invention, input datawhich has been generated at a transmission frequency is received in adata receiver. Each bit of the data is sampled at two or more positions,the positions being determined by respective phases of an internal clockof the receiver, to produce samples having respective sampled values.The internal clock runs independently of a transmit clock frequency, sothat there is a temporal drift of the sampling positions with respect tothe input data. Thus, over the course of many clock cycles, the samplingpositions effectively scan across the input data. A bit average based onthe sampled values for each bit is calculated, and the bit average, dueto the sample scanning across the input data, gives a very good metricof the overall signal quality of the input data.

[0013] In some preferred embodiments of the present invention, one ofthe samples of each bit, most preferably the sample farthest from edgesof the bit, is identified as an optimum sample. In calculating the bitaverage, the optimum sample value is given greater weight than the othersamples of the bit. In addition, the bit averages are preferablydecimated. The decimation is most preferably implemented according tothe temporal drift, so that there are substantially equal numbers of bitaverages used to determine a final overall signal quality, independentof a rate of the drift.

[0014] There is therefore provided, according to a preferred embodimentof the present invention, a method for measuring quality of a stream ofdata, which was transmitted in accordance with a transmit clock, themethod including:

[0015] generating samples of the stream of data at sample timesdetermined in accordance with a receive clock, which is characterized asoperating independently of the transmit clock; and

[0016] averaging values of the samples so as to generate a metricindicative of the quality of the stream of data.

[0017] Preferably, the data includes a first plurality of bits, andgenerating the samples includes generating a second plurality of thevalues for each bit of the data, and averaging the values includesaveraging the second plurality of values.

[0018] Generating the second plurality of the values preferably includesassigning a grade to each of the values, and averaging the valuesincludes weighting the metric in response to the grade.

[0019] Preferably, generating the second plurality of the values foreach bit of the data includes determining respective second pluralitiesof positions of the values for each bit of the data, and assigning thegrade includes assigning a higher grade in response to a distance of theposition of the grade from a transition edge of the bit.

[0020] Further preferably, assigning the higher grade includesdetermining a period for which the higher grade is assigned in responseto the temporal drift, and generating the samples includes generating anumber of the samples during the period that is substantiallyindependent of the temporal drift.

[0021] Preferably, averaging the values of the samples includesdecimating the averaging in response to the temporal drift, anddecimating the averaging includes generating a number of the samplesthat is substantially independent of the temporal drift.

[0022] Preferably, the receive clock is characterized by a temporaldrift relative to the transmit clock.

[0023] There is further provided, according to a preferred embodiment ofthe present invention, apparatus for measuring quality of a stream ofdata which was transmitted in accordance with a transmit clock,comprising:

[0024] a receive clock which is characterized as operating independentlyof the transmit clock;

[0025] a sample generator that is adapted to generate samples of thestream of data at sample times determined in accordance with the receiveclock; and

[0026] digital circuitry that is adapted to average values of thesamples so as to generate a metric indicative of the quality of thestream of data.

[0027] Preferably, the data includes a first plurality of bits, and thesamples consist of a second plurality of the values for each bit of thedata.

[0028] Further preferably, the digital circuitry is adapted to assign agrade to each of the second plurality of the values, and to weight themetric in response to the grade, and the digital circuitry is alsoadapted to determine respective second pluralities of positions of thevalues for each bit of the data, and to assign a higher grade inresponse to a distance of the position of the grade from a transitionedge of the bit.

[0029] Further preferably, the digital circuitry is adapted to determinea period for which the higher grade is assigned in response to thetemporal drift, to generate a number of the samples during the periodthat is substantially independent of the temporal drift, to decimateaveraging of the values in response to the temporal drift, and togenerate a number of the samples that is substantially independent ofthe temporal drift.

[0030] Preferably, the receive clock is characterized by a temporaldrift relative to the transmit clock.

[0031] The present invention will be more fully understood from thefollowing detailed description of the preferred embodiments thereof,taken together with the drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a schematic block diagram of a deserializer, accordingto a preferred embodiment of the present invention;

[0033]FIG. 2 are schematic graphs of data received by the deserializerof FIG. 1, according to a preferred embodiment of the present invention;

[0034]FIG. 3 is a schematic block diagram of an initial grading module,according to a preferred embodiment of the present invention;

[0035]FIG. 4 is a schematic block diagram of a leakage integrator,according to a preferred embodiment of the present invention;

[0036]FIG. 5 is a schematic block diagram of a single bit corrector,according to a preferred embodiment of the present invention;

[0037]FIG. 6 is a schematic block diagram illustrating an errorcorrection system, according to a preferred embodiment of the presentinvention;

[0038]FIG. 7 is a logical flow diagram which schematically illustrates aprocess carried out by the error correction system of FIG. 6, accordingto a preferred embodiment of the present invention;

[0039]FIG. 8 is a flowchart showing steps in the process of FIG. 7,according to a preferred embodiment of the present invention;

[0040]FIG. 9 is a schematic block diagram of a signal quality indicator(SQI), according to a preferred embodiment of the present invention;

[0041]FIG. 10 is a schematic block diagram of leakage integrators,according to a preferred embodiment of the present invention;

[0042]FIG. 11 shows schematic graphs of values of the final signalquality grade from the SQI of FIG. 9, for different input signals,according to a preferred embodiment of the present invention; and

[0043]FIG. 12 is a schematic block diagram of a multi-channeldeserializer, according to a preferred embodiment of the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0044] Reference is now made to FIG. 1, which is a schematic blockdiagram of a deserializer 10, and to FIG. 2, which comprises schematicgraphs of data received by the deserializer, according to a preferredembodiment of the present invention. In an analog front end 11,deserializer 10 receives incoming serial data which may be transmittedaccording to substantially any serial data protocol. Hereinbelow, by wayof example, the data is assumed to be transmitted in the form of 8 b/10b encoded data according to IEEE standard 802.3 z, as described in theBackground of the Invention. The data is received on a channel, hereinassumed to comprise two differential lines 12, although it will beunderstood that the channel may not comprise differential lines.

[0045] The data is combined in an input cell 13 as a single data stream50 of bits 54, as shown in a graph 52 (FIG. 2), and the single bitstream is fed to a sample generator 20. Bits 54 are also referred toherein as bits B1, B2, . . . , B10. A section of graph 52 is shown inmore detail in a graph 56. Data stream 50 is assumed to be transmittedat 3.125 Gb/s, so that each bit 54 of stream 50 has a nominal width of320 ps. However, it will be appreciated that the transmission rate andnominal width are examples, and that substantially any transmission rateand bit width may apply to the data received.

[0046] A free-running reference receive clock 14 driving a phase-lockedloop (PLL) oscillator 16 generates a base frequency of 625 MHz. The 625MHz base frequency is used to generate 20 substantially equally spacedphases, ph0, ph1, . . . , ph19 which are separated by 80 ps. The phasesare input to a multiplexer 18, and contiguous phases from themultiplexer are used to sample bits 54 in sample generator 20. Samplegenerator 20 effectively acts as a slicer, providing a decision of 0 or1 at each sample point.

[0047] As shown in graph 52, the 20 phases are used to sample a firstset of five bits {B1, B2, B3, B4, B5}, and are also used to sample asecond set of five bits {B6, B7, B8, B9, B10}, each bit being nominallysampled at four positions. Generator 20 thus generates a total of fortysamples in a cycle defined by the ten bits. The samples are provided inthe form of respective decisions which are transferred to a digitalcircuitry section 22, which also receives general timing signals derivedfrom clock 14 and/or PLL oscillator 16. It will be appreciated that theseparation of 80 ps is a fourth of the period of the nominal width. Itwill also be appreciated that the separation of 80 ps is chosen by wayof example, and that the phases may be separated by substantially anyintegral sub-multiple of the nominal width, the number of decisionsgenerated by generator 20 altering accordingly.

[0048] In digital circuitry 22 the forty decisions are grouped into foursampling sets A, B, C, D. Referring to FIG. 2, first set A comprises tendecisions—two decisions for each phase—generated by phases {ph0, ph4,ph8, ph12, ph16}. Sets B, C, and D respectively comprise ten decisionshaving phases {ph1, ph5, ph9, ph13, ph17}, {ph2, ph6, ph10, ph14, ph18},and {ph3, ph7, ph11, ph15, ph19}. Each sampling set is fed through oneof four substantially similar initial grading modules 24. Each module 24determines a quality of its respective sample set as a temporal grade,by comparing values of a present decision with values of adjacentdecisions. The initial grades generated in each module 24 are integratedin respective leakage integrators 26, and the integrated grades are usedin a main phase selector 28, as is described in more detail hereinbelow,to determine an optimal sampling set from amongst sampling sets A, B, C,D. Both the integrated grades supplied to main phase selector 28, and agrade determined by the selector, are thus determined by averagingdecisions of more than one phase or phase set.

[0049] The optimal sampling set, together with the original decisions,are processed in a single bit corrector 32 wherein errors that may becaused by a “high frequency” single bit occurring within a “lowfrequency” pattern are eliminated. Bits from corrector 32 are processedthrough a symbol alignment block 34, wherein symbols input todeserializer 10 are recovered. Symbols from deserializer 10 arepreferably output via an error correction block 150. Corrector 32 andblocks 34 and 150 are also described in more detail below. Mostpreferably, main phase selector 28 also provides outputs which are usedas inputs to a signal quality indicator 27, preferably comprised indeserializer 10, and described with reference to FIGS. 8, 9, and 10below.

[0050]FIG. 3 is a schematic block diagram of one of initial gradingmodules 24, according to a preferred embodiment of the presentinvention. Each module 24 operates in parallel on the ten decisions ofits sampling set, so that elements 60, 62, 68, 70, 72, 74, and 76, inthe module are replicated ten times. Elements 60 and 62 respectivelycomprise comparators, and are herein referred to as comparators 60 and62; elements 68 and 70 respectively comprise XOR gates, and are hereinreferred to as gates 68 and 70; elements 72 and 74 respectively compriseAND gates, and are herein referred to as gates 72 and 74; element 76comprises a summer and is herein referred to as summer 76.

[0051] Comparator 60 compares a decision value D(p,n), for a bit n, ofthe present phase p with a decision value D(p−1,n) of a phase prior tothe present phase. The output of comparator 60 is a first input to ANDgate 72. Comparator 62 compares decision value D(p,n) of the presentphase with a decision value D(p+1,n) of a phase after the present phase.The output of comparator 62 is a first input to AND gate 74.

[0052] Module 24 also comprises selectors 64 and 66, which receive 12decision values D(M) of a main phase M. Generation of main phase M isdescribed in more detail below. Selector 64 selects ten decision valuesD(M,n+1), corresponding to main phase decisions of a bit after bit n,and outputs the selected decisions as a first input of XOR gate 68.Selector 66 selects ten decision values D(M,n−1), corresponding to mainphase decisions of a bit before bit n, and outputs the selecteddecisions as a first input of XOR gate 70. The result of gate 68provides a second input to gate 74, and the result of gate 70 provides asecond input to gate 72.

[0053] The respective outputs of gates 72 and 74 are summed in summers76. Summers 76 thus output ten separate values, herein termed partialsums PS_(n), for each of the ten bits considered in stream 50. The tenvalues PS_(n) are summed in a second summer 78 to give one value, whichis delayed in a delay 80 before outputting a temporal grade TG(p) forpresent phase p from initial grading module 24.

[0054] The output of each module 24 may be represented by the followingequation: $\begin{matrix}\begin{matrix}{{{TG}(p)} = {\sum\limits_{n = 1}^{n = 10}{PS}_{n}}} \\{= {\sum\limits_{n = 1}^{n = 10}\begin{Bmatrix}{{( {{D( {M,{n - 1}} )} \neq {D( {p,n} )}} ) \oplus ( {{D( {p,n} )} = {D( {{p - 1},n} )}} )} +} \\{( {{D( {M,{n + 1}} )} \neq {D( {p,n} )}} ) \oplus ( {{D( {p,n} )} = {D( {{p + 1},n} )}} )}\end{Bmatrix}}}\end{matrix} & (1)\end{matrix}$

[0055] where TG(p) is the temporal grade of phase p,

[0056] D(M,n) is the decision of the main phase M for bit n,

[0057] D(p,n) is the decision of phase p for bit n, p+1, p−1 arerespectively next and prior phases to phase p, and

[0058] n+1, n−1 are respectively next and prior bits to bit n.

[0059] Each module 24 compares sample decisions of three consecutivebits, (n−1, n, n+1, where n=1, . . . ,10) . The ten results of thesecomparisons are summed, as shown by equation (1), in order to grade eachof the sampling phase sets.

[0060] Graph 56 illustrates the summation. In graph 56 bits B4, B5, andB6 are respectively assumed to have the values 0, 1, and 0, and n hasthe value 5.

[0061] Assume M=A, so that p=12, 16 and 0 for bits B4, B5, and B6.

[0062] From graph 56,

[0063] D(M,n−1)=0

[0064] D(p,n)=1

[0065] D(p−1,n)=0

[0066] D(M,n+1)=0

[0067] D(p+1,n)=1

[0068] Thus PS₅ for sampling set A, herein termed PS_(5A), is given by:

PS _(5A)=(0≠1)⊕(1=0)+(0≠1)⊕(1=1)=1  (2)

[0069] Assume M=B, so that p=13, 17 and 1 for bits B4, B5, and B6.

[0070] Then,

[0071] D(M,n−1)=0

[0072] D(p,n)=1

[0073] D(p−1,n)=1

[0074] D(M,n+1)=0

[0075] D(p+1,n)=1

[0076] Thus PS_(5B) is given by:

PS _(5B)=(0≠1)⊕(1=1)+(0≠1)⊕(1=1)=2  (3)

[0077] Assume M=C, so that p=14, 18 and 2 for bits B4, B5, and B6.

[0078] Then,

[0079] D(M,n−1)=0

[0080] D(p,n)=1

[0081] D(p−1,n)=1

[0082] D(M,n+1)=0

[0083] D(p+1,n)=1

[0084] Thus PS_(5C) is given by:

PS _(5C)=(0≠1)⊕(1=1)+(0≠1)⊕(1=1)=2  (4)

[0085] Assume M=D, so that p=15, 19 and 3 for bits B4, B5, and B6.

[0086] Then,

[0087] D(M,n−1)=0

[0088] D(p,n)=1

[0089] D(p−1,n)=1

[0090] D(M,n+1)=0

[0091] D(p+1,n)=0

[0092] Thus PS_(5D) is given by:

PS _(5D)=(0≠1)⊕(1=1)+(0≠1)⊕(1=0)=1  (5)

[0093] Each initial grading module 24 evaluates ten partial sums PS_(n),by using a total of forty samples from the ten bits being processed bythe modules. As shown by equation (1), the evaluation compares valuesgenerated by three consecutive bits (n−1, n, n+1). It will beappreciated that in order to evaluate the first bit (n=1) of a specificgroup of ten bits, values for the tenth bit of the preceding group arerequired for the evaluation. Similarly, to evaluate the tenth bit of thespecific group, values for the first bit of the following group arerequired for the evaluation. The total of 48 samples of the twelve bitsare stored in multiplexers 64 and 66.

[0094] Performing similar calculations to equations (2)-(5) for all bitsand assuming the bits alternate sequentially in value between 0 and 1,gives results for TG(p) as shown in Table II below. TABLE II Phase pTG(p) A 10 B 20 C 20 D 10

[0095] Temporal grades TG(p) form a basis for deserializer 10 to decidewhich sampling phases to use in evaluating bits (B1, . . . , B10. As isapparent from Table II, phases which are closer to transitions betweenvalues, i.e., phase A and D in the table, receive substantially lowergrades than phases which are farther from the transitions, i.e., phasesB and C. The calculations of grades thus enable the deserializer toselect a sampling phase furthest from transitions between values. Theselected sampling phase, also herein termed the main phase, is used bythe deserializer as a decoding phase, i.e., as an optimal phase at whichbits 54 are to be decoded.

[0096] It will be understood that while the examples above withreference to the graphs of FIG. 2 have used substantially ideal values,the principles of grading incoming bits as described hereinabove applyto non-ideal received bits. In the case of non-ideal bits, deserializer10 continuously grades the bits and determines a highest grade G fromamongst three adjacent phases, as is shown in equation (7) below. Exceptwhen there is a change in phase, it will be appreciated that the highestgrade phase, i.e. the main phase, will be the “center” of the threegraded phases. When there is a change in main phase, then for one cyclethe highest graded phase will be one of the non-central graded phases.

[0097] The resultant TG(p) of each initial grading module 24 isintegrated in a respective leakage integrator 26.

[0098]FIG. 4 is a schematic block diagram of leakage integrator 26,according to a preferred embodiment of the present invention. Eachintegrator 26 performs a weighted time integration of the value TG(p)received from its respective initial grading module 24. TG(p) is inputto a shifter 90, which shifts the value of TG(p) to the right by apredetermined number, preferably 2. The output of shifter 90 is a firstinput to a summer 92. The output of summer 92 is passed through aregister 96 acting as a time delay, and the output of register 96 is fedback directly to the summer. The output of register 96, after beingshifted right by the predetermined number in a shifter 94, is alsosubtracted in summer 92. The output from the integrator, after beingadjusted in a fixed point converter 98, is represented by the followingequation:

G(p,t)=G(p,t−1)−G(p,t−1)>>a+TG(p)>>a  (6)

[0099] where G(p,t) is the final grade of phase p at a

[0100] time t, and

[0101] a is the predetermined shifted right value.

[0102] Each of the four final grades is input to a main phase selector28 (FIG. 1). In each cycle of the 625 MHz clock selector 28 selects amain phase M(t+1) for a next cycle by finding a highest grade G fromthree adjacent phases of the present cycle, as shown in the followingequation:

M(t+1)=Max[G(M,t),G(M−1, t),G(M+1, t)]  (7)

[0103] The selected main phase M(t+1) is used, as shown in equation (1),as an input for determining the partial sums PS_(n). Preferably, ifthere is no clear-cut maximum in equation (7), G(M,t) is assumed to bethe maximum value.

[0104] Returning to FIG. 1, an index D1 of main phase M and an index D2of a second phase, the second phase having a grade closest to main phaseM, are transferred from main phase selector 28 to single bit corrector32. Corrector 32 also receives decisions from sample generator 20, via adelay 30. Corrector 32 uses the phase indices and decisionscorresponding to main phase M to allow a decision made by the main phaseto be overwritten in predetermined situations, usually caused byinter-symbol interference (ISI) . Typically, ISI is most troublesomewhen a single bit value is different from a train of bits on either sideof the single bit, for example 1111110111. Most preferably, a main phasedecision is overwritten if the following condition is true:

((D(M,n−1)=D(M,n)=(D(M,n+1))⊕(D(p,n)≠D(M,n))  (8)

[0105] where p may be M−1 or M+1.

[0106] Condition (8) is true if three consecutive main phase decisionsare the same, and if the central main phase decision is not the same asa phase on either side of the central main phase. The latter typicallyoccurs if the main phase “missed” a transition. If condition (8) is nottrue, the decision of the main phase is not overwritten.

[0107]FIG. 5 is a schematic block diagram of single bit corrector 32,according to a preferred embodiment of the present invention. Correctorssubstantially similar to single bit corrector 32 are most preferablyimplemented in parallel, the number of correctors preferablycorresponding to ten. Corrector 32 comprises a comparator 100 whichchecks for equality of decisions D(M,n−1), D(M,n), and D(M,n+1). Thedecisions are received via delay 30. The output of comparator 100 is afirst input to an AND gate 108. Two other substantially similarcomparators 102, 104 check respectively for inequality of decisionsD(M−1,n) and D(M,n), and decisions D(M+1,n) and D(M,n), which are alsoreceived via delay 30. D(M,n) corresponds to main phase index D1, andeither D(M+1,n) or D(M−1,n) correspond to second phase index D2. Thedecision D(M+1,n) or D(M−1,n) which does not correspond to D2 representsa third phase decision, on the opposite side of the main phase from D2.The outputs of comparators 102 and 104 are transferred to an OR gate106, which generates a second input to AND gate 108. The output of ANDgate 108, corresponding to equation (8), is exclusively ORed in a gate110 to decide if main decision D(M,n) is to be overwritten.

[0108] It will be appreciated that since the frequency of receiver clock14 and the effective frequency of the received bits may not beidentical, there may typically be drift between the sampling positionsgenerated by the clock and the received bits. Typically, there is astandard number of bits resolved per cycle, the standard in the examplesdescribed above being ten; the drift will cause, for one cycle,typically the cycle when there is a change in main phase , resolution ofone extra bit or one less bit in the cycle compared to the standardnumber of bits resolved. Thus corrector 32 may output, in each cycle ofthe receiver clock, 9, 10, or 11 bits.

[0109] Decisions from corrector 32 for phase index D1, as well asdecisions for phase D2, are transferred to symbol alignment block 34which temporarily stores the decisions as sets of D1 decisions and setsof D2 decisions. Bits 52 are preferably transmitted as symbols, alsotermed words, formed according to a predetermined coding scheme, mostpreferably the 8 b/10 b word coding scheme described in the Backgroundof the Invention. Block 34 analyzes the stored values to determineboundaries between symbols, by methods which are well known in the art,and outputs the symbols evaluated. Typically one symbol formed from theD1 decisions, herein termed W1, is output per cycle, but it will beappreciated that in a generally similar manner to corrector 32outputting one extra or one less bit per cycle, alignment block 34 maybe able to resolve and output 0, 1, or 2 symbols per cycle. A secondsymbol, formed from the D2 decisions and herein termed W2, is alsooutput from block 34. Symbols W1 and W2 are also termed candidate wordshereinbelow. It will be appreciated that, since its bits are derivedfrom main phase decisions, W1 has a significantly higher probability ofbeing correct than W2, which is derived from second phase decisions. Theproperty of the difference in probability, generated by assigning a mainphase and a second phase for each bit, is used in error correction block150.

[0110] As outlined in the Background of the Invention, encoding 8 bwords to 10 b words enables errors in reception of the 10 b words to bedetected.

[0111] Table III below shows how the errors introduced by an incorrectsingle bit in the 10 b word may be classified. TABLE III No. ClassDescription 1 The 10b word is invalid i.e., it is not present in mappingB1 or B2, Table I. 2 The 10b word belongs to an incorrect mapping,according to the disparity status of a string of 10b words alreadyreceived. 3 The 10b word belongs to a correct mapping, but causes thestring to expect a disparity switch when no switch should occur. 4 The10b word belongs to a correct mapping, but causes the string not toexpect a disparity switch when such a switch should occur.

[0112] Block 34 is most preferably implemented so as not to output 10 bwords in classification 1. Preferred embodiments of the presentinvention are implemented to correct errors in classifications 2, 3, and4, as described hereinbelow.

[0113]FIG. 6 is a schematic block diagram illustrating an errorcorrection system, according to a preferred embodiment of the presentinvention. W1 and W2 are input to error correction block 150, whichrecovers errors in the 8 b/10 b words it receives. It will beappreciated that block 150 may be implemented to recover errorsgenerated by transmission of other types of encoded signals which haveredundancy.

[0114] Block 150 maintains a multiplicity of sequences of previouslytransmitted candidate words Wx(t), Wx(t−1), . . . , Wx(t−N+1), where xmay be 1 or 2, and where N is the number of words W1, W2 comprised ineach sequence. The sequences are stored in a memory 152 in correctionblock 150. Herein, by way of example, the number of sequences is assumedto be three, and the sequences, also herein termed tracks, are referredto as T1, T2, and T3. Except as described below, track T1 in generalreceives W1, and track T2 in general receives W2. T1 is assumed to be apreferred track, and gives a final output from block 150. T2 is assumedto be a less preferred track. Track T3 is used as a reserve track.

[0115] A processor 154 in block 150 calculates a running disparity (RD)of each sequence, determining if the disparity status is positive, zero,or negative. Disparity and running disparity, and the concept of atransmitter generating strings of 10 b words having their RD maintainedwithin bounds, are described in more detail in the Background of theInvention.

[0116] As shown in Table III, errors may be classified as class 2, 3, or4. A class 2 error is immediately apparent, assuming there are no priorerrors in the string to which the word is being inserted. A class 3 or 4error may not be immediately apparent, but eventually causes a disparityerror similar to class 2. Processor 154 accommodates the differingerrors by copying tracks T1, T2, and T3 to each other, and by assigningW1 and W2 to the tracks, so as to maintain T1 as the preferred trackwith the highest probability of having correct words in the track.

[0117] As candidate words W1 and W2 are generated, processor 154 checksif the candidate words “fit” the sequences, updates the sequences, andinserts W1 and W2 into the updated sequences according to the mostprobably correct arrangement.

[0118] For example, if W1 fits T1, W2 fits T2, but neither fit T3, T1 isfirst copied to T3 since T1 is more probably correct than T2. W1 is theninserted to T1 and T3, and W2 is inserted to T2. If W1 or W2 fit T3, notracks are copied, W1 is inserted to T1, W2 is inserted to T1, andeither W1 or W2 is inserted to D3, depending which of W1, W2 fits T3. Ifboth W1, W2 fit T3, then W1 is inserted to T3, since W1 is more probablycorrect than W2. (This example is also considered with reference toTable V below.)

[0119]FIG. 7 is a schematic diagram illustrating stages in a process 160operated by error correction block 150, and FIG. 8 is a flowchart forthe process, according to a preferred embodiment of the presentinvention. Process 160 is applied by processor 154 to each candidateword as it is received from symbol alignment block 34.

[0120] In a first step 162 of the process, corresponding to a firststage 161, processor 154 receives the two possible candidate words W1and W2. Except for the case of W1=W2 words W1 and W2 may differ by oneor more bits, the probability of a specific number of bits differencedecreasing as the number increases. In most cases of a differenceexisting, the difference is one bit. Examples of possible pairs of wordsdiffering by one bit (derived from Table I) are given in Table IV below.The “difference” bit is underlined for each 10 b word. TABLE IV Positionin Table I W1/W2 Decimal 0, Second mapping 011000 1011 Decimal 6, Firstmapping 011001 1011 Decimal 188, First mapping 001110 1010 Decimal 189,First mapping 101110 1010 Decimal 196, Second mapping 001010 0110Decimal 228, Second mapping 001010 1110

[0121] In a second step 164, processor 154 utilizes Table I, stored inmemory 152, to determine to which mapping, B1 or B2, each word W1 and W2belongs.

[0122] In a third step 166, for each W1, W2 word received in step 162,processor 154 determines a respective grade G1, G2. The grade is anordered triple (Fit T3, Fit T2, Fit T1), each element of the triplecomprising a binary value of 0 or 1. A “1” indicates a “fit,” i.e., thatthe word may be inserted into the respective track T1, T2, or T3,without an error being apparent in the updated track. A “0” indicates a“no-fit,” i.e., that inserting the word would generate an error in thetrack. For example a grade (0,1,1) assigned to W1 means that W1 does notfit track T3, but does fit tracks T2 and T1. If W1=W2 then G2 isautomatically allocated the value (0,0,0).

[0123] It will be appreciated that a fit does not necessarily mean thata sequence with the inserted word has no erroneous words. A sequenceafter the word has been inserted may comprise a “hidden” errorcorresponding to a category 3 or 4 error. The error may be in theinserted word, or in a word further back in the sequence. Similarly, ano-fit does not necessarily mean that the word being inserted has anerror. The no-fit may also be the result of a sequence having a hiddencategory 3 or 4 error.

[0124] In a fourth step 168, corresponding to a second stage 163,processor 154 uses Table V below to assign which tracks replace eachother, and also into which tracks words W1 and W2 are inserted. Table Vis stored in memory 152. In the table T1→T2 means that track T1 iscopied to track T2, W1→T1 means that W1 is inserted to the head of trackT1. It will be understood that entries in the table such as

[0125] mean that the track initially labeled T1 is copied to T2, and thetrack initially labeled T2 is copied to T1, so that in this case thetracks essentially switch labels. Processor 154 copies the tracks, withtheir running disparity, as indicated in the table. TABLE V G2 G1 000001 010 011 100 101 110 111 000 T1 → T2 T2 → T1 T1 → T3 T3 → T1 T1 → T2T2 → T1 T1 → T3 T2 → T3 T3 → T2 W1 → T1 W2 → T1 W2 → T1 W2 → T1 W2 → T1W2 → T1 W2 → T1 W2 → T1 W1 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2W2 → T2 W2 → T2 W1 → T3 W2 → T3 W2 → T3 W2 → T3 W2 → T3 W2 → T3 W2 → T3W2 → T3 001 T1 → T2 T1 → T2 T1 → T3 T1 → T3 T3 → T2 T1 → T2 T1 → T3 T1 →T3 T1 → T3 T1 → T3 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 →T1 W1 → T1 W1 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 →T2 W1 → T3 W1 → T3 W1 → T3 W2 → T3 W1 → T3 W2 → T3 W2 → T3 W2 → T3 010T2 → T1 T1 → T2 T2 → T1 T2 → T1 T3 → T2 T2 → T1 T2 → T1 T2 → T1 T2 → T3T2 → T1 T2 → T3 T2 → T1 T1 → T2 T1 → T3 T2 → T3 T2 → T3 W1 → T1 W1 → T1W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T2 W2 → T2 W2 → T2W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W1 → T3 W1 → T3 W1 → T3 W2 → T3W1 → T3 W2 → T3 W2 → T3 W2 → T3 011 T1 → T3 T1 → T2 T2 → T3 T2 → T3 T2 →T3 T1 → T2 T2 → T3 T2 → T3 T2 → T3 T3 → T2 T2 → T3 W1 → T1 W1 → T1 W1 →T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T2 W2 → T2 W2 → T2 W2 →T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W1 → T3 W1 → T3 W1 → T3 W1 → T3 W1 →T3 W1 → T3 W1 → T3 W1 → T3 100 T3 → T1 T1 → T2 T3 → T1 T1 → T3 T3 → T1T1 → T2 T3 → T1 T3 → T1 T3 → T2 T3 → T1 T3 → T1 T3 → T2 T3 → T1 T1 → T3W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T2W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W1 → T3 W1 → T3W1 → T3 W2 → T3 W1 → T3 W2 → T3 W2 → T3 W2 → T3 101 T1 → T2 T1 → T2 T1 →T3 T3 → T2 T1 → T2 T1 → T3 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 →T1 W1 → T1 W1 → T1 W1 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 →T2 W2 → T2 W1 → T3 W1 → T3 W1 → T3 W2 → T3 W1 → T3 W1 → T3 W1 → T3 W2 →T3 110 T2 → T1 T1 → T2 T2 → T1 T1 → T3 T2 → T1 T2 → T1 T2 → T1 T2 → T1T2 → T1 T3 → T2 T1 → T3 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1W1 → T1 W1 → T1 W1 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2W2 → T2 W1 → T3 W1 → T3 W1 → T3 W2 → T3 W1 → T3 W1 → T3 W1 → T3 W2 → T3111 T1 → T2 T2 → T3 T2 → T3 T2 → T3 T2 → T3 T2 → T3 T2 → T3 T2 → T3 T3 →T2 T1 → T2 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 → T1 W1 →T1 W1 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W2 → T2 W1 →T3 W1 → T3 W1 → T3 W1 → T3 W1 → T3 W1 → T3 W1 → T3 W1 → T3

[0126] It will be understood that the operations listed in Table V arebased on maintaining track T1 as the track being most likely to comprisea correct string of received words. To illustrate the operations listedin Table V, consider the example described above, which corresponds to aset of four ordered pairs of triples: {(G1, G2)}={(0,0,1), (0,1,0)};{(1,0,1),(0,1,0)}; ((0,0,1), (1,1,0)); ((1,0,1), (1,1,0))}. Inspectionof the four cells of Table V corresponding to the ordered pairs showsthat the actions carried out correspond to those described above in theexample. Actions listed for other cells of Table V are generated in agenerally similar manner as those described for the cells of theexample.

[0127] In a final step 170, processor 152 outputs as a final decisionthe word that is in track T1.

[0128] It will be understood that the principles of the presentinvention may be applied to correcting erroneous words which have beenencoded in formats other than the 8 b/10 b format described above, orthat may not be encoded, and for correcting errors in words which haveone or more incorrect bits. It will be further understood that while thepreferred embodiments described above use three sequences of storedwords, other numbers of sequences may also be used. For example, thenumber of sequences may be set to four, so that there are two reservesequences, each of which may have either word W1 or W2 inserted. Allsuch numbers are assumed to be comprised within the scope of the presentinvention.

[0129] In an alternative preferred embodiment of the present inventionerror, correction block 150 does not receive two words W1 and W2 fromsymbol alignment block 34. Rather block 150 receives one word,preferably W1, from block 34 and a single bit quality value Q (FIG. 6).Most preferably, the single bit quality value is in the form of a flagassigned to a specific bit in the word received by block 150 whosequality has been assessed and which is considered to be problematic onthe basis of the assessment. It will be appreciated that in performingtheir tasks, both selector 28 and corrector 32 are able to generate ameasure of the quality of each single bit they analyze. For example, ifsingle bit corrector 32 does perform a correction using condition (8),the bit value output from the corrector may be considered to have a highprobability of being correct. Thus the bit quality of the bit valueoutput is high, and correspondingly, a bit quality for the opposite bitvalue for this bit is low. Those skilled in the art will be able toassign a bit quality for bits output from selector 28.

[0130] Preferably, if the bit quality is outside a predetermined value,so indicating that the bit may not be correct and that the bit isproblematic, bit quality Q is input to error correction block 150, mostpreferably by setting the flag if implemented. If the bit quality iswithin the predetermined value, so that the corresponding bit is assumedto be correct, no bit quality value is input to block 150, and the flagis not set.

[0131] Block 150 uses the bit quality and the symbol associated with thebit to construct a second word W2. Process 160, as described above withrespect to FIGS. 7 and 8, is then applied to W1 and W2.

[0132] As stated above, since clock 14 is not locked to a transmit clockof the incoming signal, the sampling positions of sampling phase sets A,B, C, D, (FIG. 2) may drift relative to data stream 50. As the positionsdrift, they effectively scan across the data stream. The scanning, andthe fact that a single value of G(p,t) (equation (6)) acts as a weightedaverage of signal levels at three adjacent phases, are used by preferredembodiments of the present invention to implement a signal qualityindicator 27 (FIG. 1). The signal quality indicator may beadvantageously used in place of specialized signal quality measurementequipment such as that described in the Background of the Invention.Signal quality indicator 27 receives its inputs, an index D1 of the mainphase and a grade G(p,t) of that phase, from main phase selector 28.

[0133]FIG. 9 is a schematic block diagram of signal quality indicator(SQI) 27, according to a preferred embodiment of the present invention.SQI 27 comprises a first leakage integrator 180 in series with a secondleakage integrator 182. Both integrators integrate their respectiveinputs so as to effectively smooth them. Leakage integrator 182 may beactivated by an enable signal generated by a multiplexer 184, so that inaddition to integrating its input, decimation may be performed on theoutput of SQI 27. The enable signal for the decimation is derived from amultiplexer 184, which activates the enable signal according to adecimation factor received by the multiplexer.

[0134] The decimation factor is most preferably generated automaticallyby a drift estimation block 186. Block 186 receives, from main phaseselector 28, the phase value that has been selected as the main phase.Block 186 also receives a timing signal, preferably generated from clock14, which enables the block to determine a duration of time for which aspecific phase is the main phase. During operation of deserializer 10the main phase changes because of drift of the sampling phase sets, asdescribed above. Block 186 measures a “phase time” during which aspecific phase of the sampling phase sets is chosen as the main phase.The measured phase time is approximately inversely proportional to a“drift speed” of the sampling phases on the data stream.

[0135] In order to scan across the data stream at a rate which isapproximately independent of drift speed, block 186 preferably sets thedecimation factor to be approximately inversely proportional to thedrift speed, so that the lower the drift speed the higher the decimationfactor. Block 186 thus preferably sets the decimation factor to bedirectly proportional to the phase time. In a preferred example of thepresent invention, Block 186 automatically sets the decimation factor sothat eight samples are taken from a specific phase, i.e., during thephase time. Optionally, multiplexer 184 may also receive an alternativedecimation factor, which may be input directly to the multiplexer froman operator of SQI 27. Such an operator input may be used, for example,in a case where the drift speed is very low or even substantially zero.

[0136]FIG. 10 is a schematic block diagram of leakage integrators 180,182, according to a preferred embodiment of the present invention. Apartfrom the differences described below, the operation of integrators 180and 182 is generally similar to that of integrator 26 (FIG. 4), so thatelements indicated by the same reference numerals in integrators 26,180, and 182 are generally identical in construction and in operation.In integrators 180 and 182, shifters 90 and 94 preferably shift theirinput to the right by 6, the value effectively controlling the size of a“sliding window” over which samples are integrated. Unlike integrator26, neither of integrators 180, 182 have a fixed point converter 98 attheir output. Integrator 182 also receives an enable input to shifter90, so that the shifter is activated according to the decimation factorused by multiplexer 184, and so that integrator 182 performs itsintegration only when enabled. Integrator 182 outputs a final signalquality grade.

[0137] The combination of two integrators in series, the second havingdecimation, gives sufficient averaging to substantially eliminate noiseeffects and also effectively scan across each bit of the incoming data.The two integrators give more flexible and better control of integrationparameters, as well as using less hardware than an equivalent singleintegrator providing the same functions as the two integrators.

[0138] Measurements of the signal quality grade are preferably made onincoming signals having the same data, for example, random idle signals.Such measurements on the same data may be performed, for example, duringinitial setup and adjustment of deserializer 10 and its incoming lines,when a remote transmitter may be requested to transmit specific data.

[0139]FIG. 11 shows schematic graphs of values of the final signalquality grade for different input signals, according to a preferredembodiment of the present invention. Five different input signals weresimulated and input to deserializer 10. The five signals had differentqualities, as determined by an eye opening measurement based on thesystem described in the Background of the Invention. Graphs 202, 204,206, 208, and 210 show values of the signal quality grade, as measuredby SQI 27, vs. time. It is seen that the grades for each input signalstabilize to a substantially constant value. Furthermore, the valuesobtained are substantially independent of the rate of decimationintroduced in integrator 182, and of the drift speed, even when thelatter is very low or substantially zero. Table VI shows the stabilizedgrade values, from SQI 27 for the different input signals, together withthe eye opening measurement for the signals. TABLE VI Stabilized SignalQuality Graph Grade Eye Opening Value 202 0.47 0.427 204 0.64 0.490 2060.65 0.494 208 0.72 0.525 210 0.72 0.526

[0140] Graph 212 plots the stabilized signal quality grades vs. the eyeopening values. It is seen both from Table VI and from graph 212 thatthere is a substantially linear relationship between the signal qualitygrades and the eye opening values, so that the grades provide a goodmetric of the signal quality.

[0141]FIG. 12 is a schematic block diagram of a multi-channeldeserializer 230, according to a preferred embodiment of the presentinvention. Multi-channel deserializer 230 comprises a plurality ofseparate deserializers 232. Apart from the differences described below,the operation of each deserializer 232 is generally similar to that ofdeserializer 10, so that elements indicated by the same referencenumerals in both deserializers 10 and 232 are generally identical inconstruction and in operation. Preferably, none of analog sections 11 ofdeserializers 232 have clock 14, PLL oscillator 16, or multiplexer 18.Rather multi-channel deserializer 230 comprises a phase generation block234, comprising a single clock 264, a PLL oscillator 256, and amultiplexer 268, respectively substantially similar to clock 14, PLLoscillator 16, and multiplexer 18. Block 234 provides twenty phases ph0,ph19, substantially as described above with reference to FIG. 1, to eachof sample generators 20 in deserializers 232, and general timing signalsto each of their digital circuitry 22. Alternatively, instead of phasegeneration block 234, one of analog sections 11 in a specificdeserializer 232 comprises single clock 264, PLL oscillator 256, andmultiplexer 268, which generate the twenty phases and general timingsignals for the deserializer, and which provide the twenty phases andtiming signals to the other analog sections 11 and digital circuitrysections 22 respectively of the other deserializers 232.

[0142] Each deserializer 232 receives a channel A, B, C, of data, andde-serializes its respective data stream substantially as describedabove for deserializer 10. It will be appreciated that multi-channeldeserializer 230 is able to deserialize substantially any number ofchannels of incoming serial data, one deserializer 232 for each channel,using only one PLL clock. Multi-channel deserializer 230 thus savessignificant numbers of components, as well as significantly reducing thecomplexity and difficulty of their arrangement, compared tomulti-channel deserializers comprising more than one PLL clock,typically one per channel plus a synchronizing PLL clock, and which mayalso require elastic buffers. It will be appreciated that multi-channeldeserializers such as deserializer 230, when implemented on a singledie, have significant improvements in yields compared to deserializershaving multiple PLL clocks, since any single PLL failure leads tofailure of the whole deserializer. Furthermore, it will be apparent thatthere is no requirement to synchronize the one PLL clock ofmulti-channel deserializer 230 to the incoming data channels, and thatthe incoming data channels to the deserializer may be transmitted withdifferent clocks.

[0143] It will thus be appreciated that the preferred embodimentsdescribed above are cited by way of example, and that the presentinvention is not limited to what has been particularly shown anddescribed hereinabove. Rather, the scope of the present inventionincludes both combinations and subcombinations of the various featuresdescribed hereinabove, as well as variations and modifications thereofwhich would occur to persons skilled in the art upon reading theforegoing description and which are not disclosed in the prior art.

1. A method for measuring quality of a stream of data, which wastransmitted in accordance with a transmit clock, the method comprising:generating samples of the stream of data at sample times determined inaccordance with a receive clock, which is characterized as operatingindependently of the transmit clock; and averaging values of the samplesso as to generate a metric indicative of the quality of the stream ofdata.
 2. A method according to claim 1, wherein the data comprises afirst plurality of bits, and wherein generating the samples comprisesgenerating a second plurality of the values for each bit of the data,and wherein averaging the values comprises averaging the secondplurality of values.
 3. A method according to claim 2, whereingenerating the second plurality of the values comprises assigning agrade to each of the values, and wherein averaging the values comprisesweighting the metric in response to the grade.
 4. A method according toclaim 3, wherein generating the second plurality of the values for eachbit of the data comprises determining respective second pluralities ofpositions of the values for each bit of the data, and wherein assigningthe grade comprises assigning a higher grade in response to a distanceof the position of the grade from a transition edge of the bit.
 5. Amethod according to claim 4, wherein assigning the higher gradecomprises determining a period for which the higher grade is assigned inresponse to the temporal drift, and wherein generating the samplescomprises generating a number of the samples during the period that issubstantially independent of the temporal drift.
 6. A method accordingto claim 1, wherein averaging the values of the samples comprisesdecimating the averaging in response to the temporal drift.
 7. A methodaccording to claim 6, wherein decimating the averaging comprisesgenerating a number of the samples that is substantially independent ofthe temporal drift.
 8. A method according to claim 1, wherein thereceive clock is characterized by a temporal drift relative to thetransmit clock.
 9. Apparatus for measuring quality of a stream of datawhich was transmitted in accordance with a transmit clock, comprising: areceive clock which is characterized as operating independently of thetransmit clock; a sample generator that is adapted to generate samplesof the stream of data at sample times determined in accordance with thereceive clock; and digital circuitry that is adapted to average valuesof the samples so as to generate a metric indicative of the quality ofthe stream of data.
 10. Apparatus according to claim 9, wherein the datacomprises a first plurality of bits, and wherein the samples comprise asecond plurality of the values for each bit of the data.
 11. Apparatusaccording to claim 10, wherein the digital circuitry is adapted toassign a grade to each of the second plurality of the values, and toweight the metric in response to the grade.
 12. Apparatus according toclaim 11, wherein the digital circuitry is adapted to determinerespective second pluralities of positions of the values for each bit ofthe data, and to assign a higher grade in response to a distance of theposition of the grade from a transition edge of the bit.
 13. Apparatusaccording to claim 12, wherein the digital circuitry is adapted todetermine a period for which the higher grade is assigned in response tothe temporal drift, and to generate a number of the samples during theperiod that is substantially independent of the temporal drift. 14.Apparatus according to claim 9, wherein the digital circuitry is adaptedto decimate averaging of the values in response to the temporal drift.15. Apparatus according to claim 14, wherein the digital circuitry isadapted to generate a number of the samples that is substantiallyindependent of the temporal drift.
 16. Apparatus according to claim 9,wherein the receive clock is characterized by a temporal drift relativeto the transmit clock.